Tuesday, 18 October 2016

JFET CHARACTERISTICS



JFET CHARACTERISTICS (16m)
JFET Drain-To-Source Voltage Variation
For a constant vGG, the effect of vDD variation may be illustrated as follows:
ô€‚¾ vDD must be greater than zero for current to flow in the direction defined in an n-channel JFET. The applied vDD, or the voltage between drain and source (ground) appears as a voltage drop across the length of the channel, with the voltage increasing along the channel from source to drain (i.e., vDS=0 at the source, vDS=vDD at the drain). We’re also going to assume a constant doping so that the voltage variation in the channel is linear.
􀂾 When vDD is very small, the voltage variation in the channel is very small and it has no effect on the channel shape. For this case, the depletion region is only due to the pn junction.
􀂾 As vDD increases, the increasing potential at the drain reverse biases the pn junctions. Since the voltage drop across the channel increases from source to drain, the reverse bias of the pn junction also increases from source to drain. Since the depletion region is a function of bias, the depletion region also gets wider from source to drain, causing the channel to become tapered. The current still increases with increasing vDD, however there is no longer a linear relationship between vDD and iD since the channel resistance is a function of its width.
􀂾 Further increases in vDD, result in a more tapered shape to the channel and increasing nonlinearities in the iD-vDD relationship.
ô€‚¾ This process continues until a vDS is reached where the depletion regions from the pn junctions merge. Analytically, this occurs when the gate-to-drain voltage vGD is less than some threshold VP (note that some sources denote the threshold as VT) and is known as the pinch-off point. At this point, the drain current saturates and further increases in vDS result in little (ideally zero) change in iD. For the case vGG=vGS=0, the drain current at pinch-off is called the drain-source saturation current, IDSS. Operation beyond the pinch-off point (vDS > vGS – VP for an n-channel device) defines the normal operating or saturation region of the JFET. 
JFET Gate-To-Source Voltage Variation
In the figure, the increasing width of the pn junction depletion region  is due to the increasing reverse bias of the junction resulting from the application of a negative vGG of increasing magnitude. As the depletion widths increase, the channel width decreases, resulting in a lower conductivity (higher resistivity) of the channel. As vGS is made more negative (for an n-channel device), a value of vGS is reached for which the channel is completely depleted (no free carriers) and no current will flow regardless of the applied vDS. This is called the threshold, or pinch-off, voltage and occurs at vGS=VGS(OFF). The threshold voltage for an n-channel JFET is negative (VP < 0).
 Output characteristic V-I curves of a typical junction FET.
 
The characteristics curves example shown above, shows the four different regions of operation for a JFET and these are given as:
Ohmic Region - When VGS = 0 the depletion layer of the channel is very small and the JFET acts like a voltage controlled resistor.
Cut-off Region - This is also known as the pinch-off region were the Gate voltage, VGS is sufficient to cause the JFET to act as an open circuit as the channel resistance is at maximum.
Saturation or Active Region - The JFET becomes a good conductor and is controlled by the Gate-Source voltage, ( VGS ) while the Drain-Source voltage, ( VDS ) has little or no effect.
Breakdown Region - The voltage between the Drain and the Source, ( VDS ) is high enough to causes the JFET's resistive channel to break down and pass uncontrolled maximum current.
Drain current in the active region.
Note that the value of the Drain current will be between zero (pinch-off) and IDSS (maximum current). By knowing the Drain current ID and the Drain-Source voltage VDS the resistance of the channel ( ID ) is given as:

Drain-Source channel resistance.
Where: gm is the "transconductance gain" since the JFET is a voltage controlled device and which represents the rate of change of the Drain current with respect to the change in Gate-Source voltage.

Shorted gate drain current (Idss)
It is the drain current with source short circuited to gate Vgs =0 and drain voltage Vds equal to pinch off voltage.it is called zero bias current.
The drain current raise rapidly at first and then levels off at pinch off voltageVp. The drain current has now reached the maximum value Idss when Vds is increased beyond Vp the depletion layers expand at the top of the channel. the channel now acts as current limiter and  holds drain current constant at Idss

Pinch off voltage Vp
It is the minimum drain source voltage at which the drain current essentially becomes constant
Gate – source cut off voltage Vgs (off)
It is the gate source voltage where the channel is completely cut off and the drain current becomes zero.
JFET Transfer Characteristics


After the JFET reaches saturation, iD remains relatively constant with a very small slope for further increases in vDS (the slope of the curves would be zero for an ideal device).

To operate in the linear region, it is standard practice to define the dc bias current at the Q-point as between 30% and 70% of IDSS. This locates the Q-point in the most linear region of the characteristic curves. To locate the Q-point near the center of the linear operating region, your author suggests using IDQ=IDSS/2 and VGSQ=0.3VP. As vDS continues to increase, a point is reached when the drain-to-source voltage becomes so large that avalanche breakdown occurs at the drain end of the gate-channel junction. At the breakdown points, shown by dashed lines in the figure, iD increases sharply with negligible increases in vDS. The value of vDS denoted BVGDS is the breakdown voltage of the pn junction (i.e., when vGS=0). As can be seen in the figure above, the breakdown voltage is also a function of vGS – as the magnitude of vGS increases (more negative for n-channel and more positive for p-channel) the breakdown voltage decreases.
Trans conductance:
Trans conductance is defines how the drain current is controlled by the gate source voltage. It is aslo called as forward transfer admittance.



Its unit is Siemens. (S)



 

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